Semiconductor circuits are manufactured by fabricating a plurality of dies on a single wafer. The dies on the wafer, also referred to as "chips", typically have the same circuit pattern to minimize complexity during wafer fabrication. An important factor in maximizing yield and maintaining quality control during manufacturing is accurate detection of defects on the dies. A defect can be a deformity such as extra or missing material in a layer of a circuit, typically caused by contaminants such as an unwanted particle or droplet of liquid which falls on the wafer during the manufacturing process.
Defect scanners have been developed to provide improved accuracy in identifying the size and location of defects. For example, light scattering defect scanners detect defects on a circuit pattern of a die by directing a beam of light at the circuit pattern at an angle of 45.degree. incident to the wafer surface and perpendicular to the circuit pattern of the die. Any object on the circuit pattern at an angle other than 90.degree. will generate a scattering light pattern and thus be considered a defect. Defect scanners using pattern matching techniques compare a circuit pattern with corresponding circuit patterns of neighboring dies, such that any variations in the detected patterns are considered defects.
The current tolerance for conventional light scattering defect scanners is .+-.20 micrometers (.mu.m) in identifying a defect coordinate on a wafer, and the current tolerance for pattern matching defect scanners is .+-.12 .mu.m in identifying the defect coordinate on a wafer. However, current fabrication techniques have produced dies having circuit patterns on the order of one micron (1 .mu.m). Hence, the existing scanners cannot adequately detect defects on dies having 1 .mu.m circuit patterns because the scanners have insufficient sensitivity, resolution, or accuracy to measure the 1 .mu.m circuit patterns.
Prior attempts to calibrate the sensitivity of defect scanners have included randomly depositing predetermined sized particles on the wafer. This technique, however, does not improve the accuracy of the scanners relative to each dies because the deposited particles are randomly distributed on the dies. In addition, the depositing of predetermined sized particles on a wafer is a destructive process and cannot be used for defect scanning during wafer fabrication. Finally, the use of particles having the same size precludes the automatic adjustment of the sensitivity of the defect scanning tools.
The defect scanners of the prior art also are unable to distinguish between null defects and killer defects. Null defects do not affect the operation or yield of a circuit pattern, and killer defects render the circuit pattern inoperable, requiring scrapping of the dies. An example of a null defect is a particle falling on a dies during wafer fabrication that lands at a portion of the die that is separate from the circuit pattern. Another example of a null defect is a particle landing on a redundant portion of the circuit pattern or a noncritical portion of the circuit pattern, enabling the continued use of the integrated circuit after the manufacturing of the dies is completed.
Conventional defect detecting techniques involve visual inspection of the dies using a microscope, where a technician visually inspects representative samples of the wafer to identify defects. Such techniques are inefficient because too much technician time is necessary for inspection. such techniques also are inadequate in accurately detecting defects because a technician may misjudge the position of a defect on the circuit pattern. A technician may also erroneously scrap a wafer due to a large defect that is not a killer defect, but rather a null defect. The technician also cannot anticipate the effect of a defect on subsequent layers during the fabrication process.
Finally, visual inspection does not provide a reliable collection of data for failure analysis. Hence, quality control efforts are hindered because there is no accurate arrangement for identifying critical areas of the circuit pattern having a high failure rate due to an unusually high sensitivity to defects.